The present invention relates, in general, to a phased array and more particularly to a monolithic gallium arsenide (GaAs) phased array having gold (Au) post interconnects for interconnecting multiple layers of the phased array.
Phased arrays have numerous applications in military systems such as smart munitions and multi-mission surveillance radars. An efficient phased array system must perform real-time scanning for target detection, identification, tracking, covert communication and threat warning from all directions, and at the same time it must conform to the vehicle to minimize the radar cross section. Hence, a very thin, low-cost phased array system is a desirable solution to the problem of a conformal array integrated into the vehicle's skin. The array's required almost panoramic field of vision sets constraints on the element-to-element spacing and, often, the distribution network and control circuitry must be built on a layer different from the transmit/receive module (herein referred to as T/R module) layer.
One of the most challenging problems in the assembly of such an array is the layer-to-layer interconnections that need to be made to connect processing circuitry and distribution network lines to the active T/R modules that are, in turn, coupled to the radiating elements. Other difficulties include the support structures that separate the different layers, and the coolant passages for excess heat removal.
Existing methods of interconnecting different layers include microcoaxial lines for the RF connections and ceramic walls with perimeter interconnects for the DC and control connections. Fiber optical cables have also been considered. The above methods, however, are very tedious and expensive to implement, and therefore disadvantageous.
Another existing approach that avoids multi-layer interconnections is the "stacked motherboard" approach which utilizes one motherboard of a dielectric material on which all the necessary distribution network, DC bias and control lines are printed, with the T/R module chips placed on the motherboard. The complete array is then formed by stacking several of these motherboards in shelves. This approach, however, is disadvantageous because it suffers from having a considerably thicker size than the multi-layer approach, and its hybrid assembly is very expensive and time-consuming.